1. Field of the Invention
This invention generally relates to semiconductor devices, and more specifically, to tri-gate field effect transistors.
2. Background Art
Due to the increasing difficulty in shrinking complementary metal-oxide-semiconductor (CMOS) transistor gate lengths while simultaneously controlling leakage current, the traditional single-gate metal-oxide-semiconductor field-effect transistor (MOSFET) structure may be supplanted by dual- or triple-gate MOSFET structures. These structures, by increasing the gate's control of the channel potential, allow greater ability to turn off MOSFETs with ultra-short channel lengths. Of the various multi-gate MOSFETs structures explored in recent years, the most promising in terms of manufacturability and performance are typically variations of the so-called “FinFET” structure. In these devices, strip or “fin” of silicon is formed, and subsequently the gate material is deposited and etched, so that the resulting gate surrounds the fin on the three exposed sides. The channel region of the device is located in the fin. Because the gate electrode and the gate dielectric surround the semiconductor body on three sides, the transistor essentially has three separate channels and gates.
Tri-gate device structures, in particular, are receiving substantial attention as a candidate for 22 nm technologies and beyond. Because there are three separate channels formed in the semiconductor body, the semiconductor body can be fully depleted when the transistor is turned on, thereby enabling the formation of a fully depleted transistor with gate lengths of less than 30 nanometers without requiring the use of ultra-thin semiconductor bodies or requiring photolithographic patterning of the semiconductor bodies to dimensions less than the gate length of the device.
Tri-gate device structures offer better electrostatic control, permitting gate length scaling. In addition, the current available per planar layout is potentially increased, as the sidewalls are gated regions.